1. Field of the Invention
The present invention relates, in general, to testing of integrated circuits, and, more specifically, to a method of collecting in real time memory failure information for memories tested using an embedded memory test controller.
2. Description of Related Art
Memory failure information can be used to monitor and improve the quality of an integrated circuit manufacturing process. This is done by diagnosing and correlating functional failures to defects in the circuit introduced during manufacturing. The defects can in turn be associated with a certain step of the manufacturing process. Modifications can be made to this manufacturing step by using different settings for temperature, duration, dust control, and the like. If these modifications are not sufficient or possible, the circuit design might have to be changed to be more tolerant of this type of defect. One type of design modification is the introduction of redundant memory cells that can be substituted for defective memory cells.
Conventional diagnosis methods transfer detailed information about all failures off-chip to a tester for analysis. It is difficult or even impossible to do so in real time because of the bandwidth required. There are two aspects of the bandwidth problem.
A first aspect relates to the amount of information to be sent. One bit of information is required for every memory bit read. Memories often have a large number of bits (16 to 256) that are read simultaneously. This number of bits is multiplied by the number of words and by the number of read operations. This large amount of detailed information could be transferred off-chip by means of a large number of pins corresponding to the number of bits in a word. However, it is not desirable or even possible to do so. As is well known in the art, it is important to minimize the number of pins in order to reduce test cost.
A second aspect of the bandwidth problem relates to the rate at which the detailed information can be exported to a tester. Memories now operate at clock rates that exceed tester interface clock rates and is one of the reasons why embedded test controllers are used to perform memory testing. Embedded test controllers can determine whether a memory is good or bad. However, raw detailed failure information cannot be transferred without transformation because the information is generated faster than a tester can accept. One possible solution is to use a demultiplexer to reduce the rate of transfer to the tester. However, this requires multiplying the number of pins used to transfer the failure information by the ratio of the memory clock rate to the tester interface clock rate. This ratio can be as high as 10.
FIG. 1 illustrates an example of a simple memory 10 which contains defects indicated by black squares. Memory 10 contains four bit words. The bits are organized into bit arrays, labeled Bit 0 through Bit 3, comprised of eight columns and 16 rows, providing 128 words (8 columns times 16 rows) of four bits each for a total of 512 bits. The rows are arranged into two segments, labeled Segment 1 and Segment 2. Each bit of an array is accessed by applying a row address to a row decoder 12 and a column address to a column decoder 14. Four bits are used to access one of the 16 rows and three bits are used to access one of the eight columns of each bit-array. Several memories can be grouped together to form a larger memory. Individual memories are designated as banks. Banks can be used to increase the width of the memory, i.e. to add more bits per word. In this case, no additional address bits are necessary. Banks can also be used to increase the depth of the memory, i.e., to add more words. If the memory included banks, bank address bits would be used to select which bank is accessed. It will be understood by those skilled in the art that memories usually have many more rows, columns and banks than that shown in the figure and indicated above. Memory 10 illustrates one of several memory architectures and access mechanisms.
FIG. 2 shows a representative set of failure patterns that are of interest from a process monitoring point of view because each pattern can be associated with the presence of specific defects. Failure patterns generally consist of single cell failures, 2-cell failures, partial/full/two column failures and row failures. Other classifications are possible.
Chen et al, in a paper entitled “Enabling Embedded Memory Diagnosis via Test Response Compression”, 19th IEEE VLSI Test Symposium (VTS 2001) (see also Chen et al. PCT Patent Application WO 01/67463 A1 published on Sep. 13, 2001 for “Method and Apparatus for Diagnosing Memory using Self-Testing Circuits”), disclose a compression technique which uses a 6-bit output per group of fail vector. Bits of the fail vectors are combined in various ways along rows (AND, OR, 2OR (2 or more failures in the word)), columns (MaskedAND, MaskedOR, Repeat) and diagonals (XOR). Primary disadvantages of the method are that the method requires high-speed outputs, and the complexity of the functions requires splitting a fail vector into many groups, thereby increasing the number of pins that need to be connected to a tester.
Schanstra et al., in a paper entitled “Semiconductor Manufacturing Process Monitoring Using BIST for Embedded Memories” and published in the Proceedings of the International Test Conference, Oct. 18-23, 1998, disclose a method which uses several registers to collect failure information during the execution of a memory test. The registers are only inspected and exported at the end of the memory test. The registers include a fault counter, a column fault capture unit, and an address capture unit for isolated faults. The drawbacks of this method are that it does not capture information respecting faulty rows and the results of a column fault capture unit are corrupted in the presence of faulty rows. The method is restricted to algorithms that use column access mode only and requires too many registers because the test controller must accumulate the failure information until the end of the test instead of sending failure information as it is available, i.e., in real time.
Clearly, a different method is needed to compress failure information that needs to be transferred without sacrificing the ability of extracting relevant failure information. The level of resolution of the information can be traded off based on the application for which the information is required. For example, for yield analysis, it is sufficient to know the failure density (e.g., the number of failures in a column or row) for any density of failures, whereas, for repair analysis, it is necessary to know the location of individual failures more precisely when the density is low. The method of the present invention supports such trade-off. As will be seen, the present invention takes advantage of the memory structure and certain characteristics of conventional memory tests to generate failure summaries.